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CS3511
Stereo 10 W High-efficiency Class-D Audio Power Amplifier
Features
Closed-loop Advanced Architecture True Spread Spectrum Modulation Premium Quality Audio Amplification
Common Applications
Active Speakers Portable Media Player Docking Stations Mini/Micro Shelf Systems Digital Televisions
- - -
99 dB Dynamic Range - System Level 0.025% THD+N @ 5 W - System Level -104 dB Channel Separation
General Description
The CS3511 is a high-efficiency class-D PWM amplifier that integrates on-chip over-current, under-voltage, over-temperature protection, and error reporting. An onboard regulator generates a 5 VDC supply used to power the internal low-voltage analog and digital circuitry. The low RDS(ON) outputs can source peak currents up to 2.7 A, deliver high efficiency, allow a small device package, and lower power supply voltage levels. The CS3511 is available in a 32-pin QFN package in Commercial grade (-10C to +70C). The CRD3511 customer reference design is also available. Please refer to "Ordering Information" on page 25 for complete ordering information.
Four Selectable Amplifier Gain Settings Integrated Protection and Automatic Recovery
for Over-current, Under-voltage, and Thermal Overload
Single-supply Operation (Typ. = 9-12 V) No Bootstrap Capacitors Required Low-power Standby Mode Supports Differential or Single-ended Inputs Thermally Enhanced 32-pin, 6 x 6 mm QFN
Package Requires No External Heat Sink
Analog Power
Digital Power
5V Regulator
12 V
Positive Input Channel 1 Negative Input MUTE SLEEP STATUS Charge Pump GAIN0 GAIN1 Gain Control
VP Channel 1
Processing and Modulation
Gate Drive
Positive Output Negative Output
Positive Input Channel 2 Negative Input
Processing and Modulation
Channel 2 Gate Drive Positive Output Negative Output PGND
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Copyright Cirrus Logic, Inc. 2009 (All Rights Reserved)
DEC `09 DS845F1
CS3511
TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 4 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 9 DIGITAL INTERFACE SPECIFICATIONS ............................................................................................. 9 DIGITAL I/O PIN CHARACTERISTICS ............................................................................................... 10 3. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 11 4. APPLICATIONS ................................................................................................................................... 13 4.1 CS3511 Input Stage ....................................................................................................................... 13 4.2 Dynamic DC Offset Calibration ...................................................................................................... 13 4.3 CS3511 Amplifier Gain .................................................................................................................. 14 4.4 MUTE Pin ....................................................................................................................................... 14 4.5 SLEEP Pin ..................................................................................................................................... 14 4.6 Power Up and Power Down Sequence .......................................................................................... 14 4.6.1 Recommended Power-Up Sequence .................................................................................... 14 4.6.2 Recommended Power-Down Sequence ............................................................................... 15 4.7 Protection Circuits .......................................................................................................................... 15 4.7.1 Under-Voltage Protection ...................................................................................................... 15 4.7.2 Over-Temperature Protection ................................................................................................ 15 4.7.3 Over-Current Protection ........................................................................................................ 15 4.8 Integrated 5 V Regulator ................................................................................................................ 15 4.9 Power Dissipation De-Rating ......................................................................................................... 15 4.10 Performance Measurements of the CS3511 ................................................................................ 16 4.11 Full-Bridge Output Filter ............................................................................................................... 16 5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT ....................................................................... 17 5.1 Power Supply and Grounding ........................................................................................................ 17 5.1.1 Maximum Supply Voltage ...................................................................................................... 17 5.2 QFN Thermal Pad .......................................................................................................................... 17 5.3 Layout Considerations ................................................................................................................... 17 6. TYPICAL AUDIO PERFORMANCE PLOTS ........................................................................................ 18 7. PARAMETER DEFINITIONS ................................................................................................................ 22 8. PACKAGE DIMENSIONS .................................................................................................................... 23 9. THERMAL CHARACTERISTICS ......................................................................................................... 24 9.1 Thermal Flag .................................................................................................................................. 24 10. ORDERING INFORMATION .............................................................................................................. 25 11. REVISION HISTORY .......................................................................................................................... 26
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CS3511
LIST OF FIGURES
Figure 1.Typical Connection Diagram - Stereo Amplifier with Differential Inputs ...................................... 11 Figure 2.Typical Connection Diagram - Stereo Amplifier with Single-Ended Inputs ................................. 12 Figure 3.CS3511 Input Stage .................................................................................................................... 13 Figure 4.Output Filter ................................................................................................................................ 16 Figure 5.THD+N vs. Output Power (RL= 8 ) .......................................................................................... 18 Figure 6.THD+N vs. Output Power (RL= 6 ) .......................................................................................... 18 Figure 7.THD+N vs. Output Power (RL= 8 ) .......................................................................................... 18 Figure 8.THD+N vs. Output Power (RL= 6 ) .......................................................................................... 18 Figure 9.THD+N vs. Output Power (RL= 8 ) .......................................................................................... 18 Figure 10.THD+N vs. Output Power (RL= 6 ) ........................................................................................ 18 Figure 11.Supply Current vs. POUT (RL= 8 ) ......................................................................................... 19 Figure 12.Supply Current vs. POUT (RL= 6 ) ......................................................................................... 19 Figure 13.THD+N vs. Frequency (RL= 8 ) ............................................................................................. 19 Figure 14.THD+N vs. Frequency (RL= 6 ) ............................................................................................. 19 Figure 15.Frequency Response (POUT = 1 , RL= 8 ) ......................................................................... 19 Figure 16.Frequency Response (POUT = 1 , RL= 6 ) ......................................................................... 19 Figure 17.Crosstalk vs. Frequency (RL= 8 ) ........................................................................................... 20 Figure 18.Crosstalk vs. Frequency (RL= 6 ) ........................................................................................... 20 Figure 19.Output FFT (POUT = 1 W, RL= 8 ) ........................................................................................ 20 Figure 20.Output FFT (POUT = 1 W, RL= 6 ) ........................................................................................ 20 Figure 21.Output FFT (POUT = 5 W, RL= 8 ) ........................................................................................ 20 Figure 22.Output FFT (POUT = 5 W, RL= 6 ) ........................................................................................ 20 Figure 23.Efficiency (RL= 8 ) .................................................................................................................. 21 Figure 24.Efficiency (RL= 6 ) .................................................................................................................. 21
LIST OF TABLES
Table 1. I/O Power Rails ........................................................................................................................... 10 Table 2. Low-Pass Filter Components ...................................................................................................... 16
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CS3511 1. PIN DESCRIPTIONS
BIASCAP
AGND
AGND
IN1-
32
31
30
29
28
27
26
IN225
V5A
C1
C2
IN1+ V5D GAIN0 DGND REF SLEEP MUTE STATUS
1 2 3 4
24 23 22 21
IN2+ AGND GAIN1 5VGEN VP DCAP CPUMP PGND
Thermal Pad
5 6 7 8 9 10 11 12 13 14 15 16 20 19
Top-Down (Through Package) View 32-Pin QFN Package
18 17
OUT1-
OUT1+
OUT2-
Pin Name
IN1+ IN1IN2+ IN2V5D GAIN0 GAIN1 DGND REF SLEEP MUTE
#
1 32 24 25 2 3 22 4 5 6 7
Pin Description
Differential Analog Input (Input) - Differential Audio Signal Inputs for channel 1 and channel 2. Digital Power (Input) - Supply for digital logic. Connect to 5VGEN. Gain (Input) - Gain select bits. GAIN0 is the least significant bit. Digital Ground (Input) - Ground reference for the internal logic and digital I/O. Reference (Output) - Internal reference voltage. Sleep (Input) - When set to logic high, device enters low power mode. If not used, this pin should be grounded. Mute (Input) - When set to logic high, both amplifiers are muted and in Idle Mode. When low (grounded), both amplifiers are fully operational. If not used, this pin should be grounded. Status (Output) - A logic high output indicates over-current or under-voltage condition, thermal overload, that an output is shorted to ground or to another output, that the device is in low power mode (the SLEEP pin is high), or that the device is in reset. A logic low state indicates that the CS3511 is ready to output audio.
STATUS
8
4
OUT2+
VP
PGND
PGND
VP
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CS3511
OUT1+ OUT1OUT2+ OUT2VP 9 12 16 13 10 15 20 11 14 17 18 19 21 23 27 30 24 25 26 31 28 29 Differential PWM Output (Output) - Differential PWM Outputs for channel 1 and channel 2.
High Voltage Power (Input) - Supply pins for high current H-bridges.
PGND CPUMP DCAP 5VGEN AGND IN2+ IN2C2 C1 V5A BIASCAP Thermal Pad
Power Ground (Input) - High current ground for analog outputs. Charge Pump Input (Input) - Input pin for charge pump. Charge Pump Switching Pin (Output) - Free-running 350 kHz square wave between VP and ground. 5 Volt Generator (Output) - Regulated 5 VDC source used to supply power to the input section (pins 2 and 28). Analog Ground (Input) - Connect all pins together directly at the thermal pad of the CS3511. Negative Analog Input (Input) - Negative Audio Signal for channel 2 and channel 1, respectively. Pop Minimization Capacitor (Input) - External capacitor used to reduce turn on/off pops. Analog Power (Input) - Supply for analog circuitry. Connect to 5VGEN. Analog Input Bias (Input) - Input stage bias voltage. Thermal Pad (Input) - Thermal relief pad for optimized heat dissipation. Connect to PGND. See "QFN Thermal Pad" on page 17 for more information.
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CS3511 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
AGND = DGND = PGND = 0 V; All voltages with respect to ground. (Note 1) Parameters DC Power Supply
Supply Voltage VP TA TJ 8.5 -10 -10 12 13.2 +70 +150 V C C
Symbol
Min
Typ
Max
Units
Temperature
Ambient Temperature Junction Temperature
Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability.
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = PGND = 0 V; All voltages with respect to ground. Parameters DC Power Supply
Outputs Switching and Under Load No Output Switching (Note 2) VP VP Iin VIND TA Tstg -0.3 -0.3 -20 -65 13.2 14.0 10 V5D + 0.3 +85 +150 V
Symbol
Min
Max
Units
Inputs
Input Current Digital Input Voltage (Note 3) (Note 4) mA V C C
Temperature
Ambient Operating Temperature (power applied) Storage Temperature
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Notes: 2. The outputs will stop switching at the VP Under-Voltage Error Falling Trigger Point. See "DC Electrical Characteristics" on page 9. 3. Any pin except supplies. Transient currents of up to 100 mA on the INxx pins will not cause SCR latch-up. 4. The maximum over/under voltage is limited by the input current.
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CS3511 AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): AGND = DGND = PGND = 0 V; All voltages with respect to ground; TA = 25C; VP = 12 V; RL = 8 full-bridge; GAIN1 = 0, GAIN0 = 1; 10 Hz to 20 kHz Measurement Bandwidth; Performance measurements taken with a 997 Hz sine wave and AES17 measurement filter; Stereo Full-Bridge measurements taken through the Full-Bridge Output Filter shown in Figure 4 on page 16. Parameters Differential Input (Note 5)
Output Power (Continuous Average/Channel) (Note 6) PO
Symbol
Test Conditions
THD+N = 1% THD+N = 7% THD+N = 10% RL = 8 RL = 6 RL = 8 RL = 6 RL = 8 RL = 6
Min
-
Typ
7.6 9.5 9.0 11.2 9.5 11.8 0.019 0.025 99 96 99 96 104 13.6 19.5 23.8 27.3 7.6 9.5 9.0 11.1 9.5 11.8 0.019 0.027 99 96 99 96 102 13.5 19.5 23.8 27.2
Max
-
Units
W W W W W W % % dB dB dB dB dB dB dB dB dB W W W W W W % % dB dB dB dB dB dB dB dB dB
Total Harmonic Distortion + Noise Dynamic Range Signal to Noise Ratio
(Note 6) (Note 7) (Note 7)
THD+N DYR SNR
PO = 1 W, RL = 8 PO = 5 W, RL = 8 A-Weighted Unweighted Inputs AC coupled to AGND A-Weighted Unweighted PO=1 W, f = 1 kHz Gain1 = 0, Gain0 = 0 Gain1 = 0, Gain0 = 1 Gain1 = 1, Gain0 = 0 Gain1 = 1, Gain0 = 1 THD+N = 1% THD+N = 7% THD+N = 10% RL = 8 RL = 6 RL = 8 RL = 6 RL = 8 RL = 6 Vin = -60 dBi
Channel Separation Amplifier Gain
CS
Single Ended Input (Note 8) Output Power (Continuous Average/Channel) (Note 6)
PO
-
Total Harmonic Distortion + Noise Dynamic Range Signal to Noise Ratio
(Note 6) (Note 7) (Note 7)
THD+N DYR SNR
PO = 1 W, RL = 8 PO = 5 W, RL = 8 A-Weighted Unweighted Inputs AC coupled to AGND A-Weighted Unweighted PO=1 W, f = 1 kHz Gain1 = 0, Gain0 = 0 Gain1 = 0, Gain0 = 1 Gain1 = 1, Gain0 = 0 Gain1 = 1, Gain0 = 1 Vin = -60 dBi
Channel Separation Amplifier Gain
CS
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CS3511
Parameters General Specifications
Efficiency Gain Matching Power Supply Rejection Ratio PSRR IHF Intermodulation Distortion Input Impedance (Note 9)
Symbol
Test Conditions
PO = 2 x 9.4 W, RL = 8 Between output channels 200 mv p-p from 20 Hz f 1 kHz, inputs AC coupled to AGND 19 kHz, 20 kHz, 1:1 (IHF), PO = 1 W Gain1 = 0, Gain0 = 0 Gain1 = 0, Gain0 = 1 Gain1 = 1, Gain0 = 0 Gain1 = 1, Gain0 = 1 MUTE = low
Min
-
Typ
86 0.1 55
Max
-
Units
% % dB
IHF-IMD
36.8 18.4 11.0 7.3 -
0.20 46.0 23.0 13.8 9.2 50 2.7 155 135 155 3
55.2 27.6 16.6 11.1 -
% k k k k mV A C C ms ms
Output Offset Voltage
(Note 10)
VOFFSET ICE TTERISE TTEFALL ton toff
PWM Output Over-Current Error Trigger Point Junction Thermal Error Rising Trigger Point Junction Thermal Error Falling Trigger Point Turn On Time Turn Off Time
SLEEP = VIL SLEEP = VIH
-
Notes: 5. All audio input signals supplied differentially to the CS3511. 6. See Figure 5 on page 18. 7. dBi is referenced to the input signal amplitude resulting in the specified output power at THD+N<1%. See "Parameter Definitions" on page 22 for more information. 8. All audio input signals supplied single ended to the CS3511 with the negative input terminated to GND through an impedance matching circuit as described in Section 4.1 on page 13. 9. Input impedance is measured between the positive (INx+) and negative (INx-) input pins of the CS3511. 10. See Section 4.2 "Dynamic DC Offset Calibration" on page 13.
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CS3511 DC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): AGND = DGND = PGND = 0 V; All voltages with respect to ground; TA = 25C; VP = 12 V; RL = 8 full-bridge; GAIN1 = 0, GAIN0 = 1; Stereo Full-Bridge measurements taken through the Full-Bridge Output Filter shown in Figure 4 on page 16. Parameters
Sleep Supply Current ICC(sleep) Mute Supply Current ICC(mute) Quiescent Current ICC
Symbol
Test Conditions
SLEEP = VIH SLEEP = VIH; no load, filter, or snubber MUTE = VIH MUTE = VIH; no load, filter, or snubber VIN = 0 V; SLEEP = VIL, MUTE = VIL VIN = 0 V; SLEEP = VIL, MUTE = VIL; no load, filter, or snubber Id = 0.5 A, TJ = 50C
Min
-
Typ
5.2 5.2 38 38 68 85
Max
-
Units
mA mA mA mA mA mA
MOSFET On Resistance (each FET) 5VGEN Nominal Voltage 5VGEN DC current source REF Nominal Voltage BIASCAP Nominal Voltage VP Under-Voltage Error Falling Trigger Point VP Under-Voltage Error Rising Trigger Point V5A Under-Voltage Error Falling Trigger Point V5A Under-Voltage Error Rising Trigger Point Charge Pump Under-Voltage Error Falling Trigger Point Charge Pump Under-Voltage Error Rising Trigger Point
RDS(ON)
-
325 5.2 30 1.2 2.5 7.56 8.08 4.1 4.3 1.55*VP 1.62*VP
-
m V mA V V V V V V
VUVVPFALL VUVVPRISE VUV5VFALL VUV5VRISE VUVCPFALL VUVCPRISE
-
DIGITAL INTERFACE SPECIFICATIONS
AGND = DGND = PGND = 0 V; All voltages with respect to ground; Unless otherwise specified. Parameters
High-Level Input Voltage (MUTE, SLEEP) High-Level Input Voltage (GAIN1, GAIN0) Low-Level Input Voltage (MUTE, SLEEP, GAIN1, GAIN0) (Note 11) Transition Time Between VIH and VIL (MUTE, SLEEP) High-Level Output Voltage (STATUS) Low-Level Output Voltage (STATUS) Input Leakage Current (MUTE, SLEEP) Input Leakage Current (GAIN1, GAIN0) (Note 11) IO = 250 A IO = 250 A (Note 11)
Symbol
VIH VIH VIL tI VOH VOL Iin Iin
Min
V5D - 2 V5D - 0.8 V5D - 0.5 -
Max
1 500 0.5 10 300
Units
V V V ns V V A A
Notes: 11. Levels between VIH and VIL are invalid. The transition period between VIH and VIL should not exceed tI.
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CS3511 DIGITAL I/O PIN CHARACTERISTICS
The logic level for each input is set by its corresponding power supply and should not exceed the maximum ratings. Power Pin Supply Number
3 22 5VD 7 6 8 35 VP 32 29 26
Pin Name
GAIN0 GAIN1 MUTE SLEEP STATUS OUT1+ OUT1OUT2+ OUT2-
I/O
Input Input Input Input Output Output Output Output Output
Driver
5.0 V 8.5 V - 13.2 V Power MOSFET 8.5 V - 13.2 V Power MOSFET 8.5 V - 13.2 V Power MOSFET 8.5 V - 13.2 V Power MOSFET Table 1. I/O Power Rails
Receiver
5.0 V; Internal 50 k pull-down 5.0 V; Internal 50 k pull-down 5.0 V 5.0 V -
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CS3511 3. TYPICAL CONNECTION DIAGRAMS
3
GAIN0 GAIN1 MUTE SLEEP STATUS AGND VP
System Control Logic
22 7 6 8 27
R1
1.0 f 1
CS3511
IN1+ IN1IN2+ IN2V5A C1 C2 BIASCAP
32
VP 10
0.1 f
Differential Analog Inputs
Note(R1=R2)
+
220uF
R2
1.0 f
R3
1.0 f 24
Differential Analog Inputs
Note(R3=R4)
OUT1+ OUT1-
9 12
R4
1.0 f 25
Full-Bridge Output Filter
(Note 1)
RL 6 to 8
Channel 1 Audio Output
28 31 26 1 f 10 f + 10 f + 1 f 29
PGND
11
VP
30
AGND
VP 15
0.1 f
+
220 uF
(Note 2)
18 1.0 f 0.1 f 19
CPUMP DCAP VP 5VGEN AGND PGND
17
OUT2+ 16 OUT213
VP
20 21 0.1 f 0.1 f 23
Full-Bridge Output Filter
(Note 1)
RL 6 to 8
Channel 2 Audio Output
PGND
14
2 5 1 f
V5D REF
20 K 1%
4
DGND
1. See Section 4.11 for typical full-bridge output filter. 2. Incorrectly connecting the external charge pump circuitry can result in permanent damage to the device. Figure 1. Typical Connection Diagram - Stereo Amplifier with Differential Inputs DS845F1 11
CS3511
3
GAIN0 GAIN1 MUTE SLEEP STATUS AGND VP
System Control Logic
22 7 6 8 27
R1
1.0 f 1
CS3511
IN1+ IN1IN2+ IN2V5A C1 C2 BIASCAP
32
VP 10
0.1 f
Single-Ended Analog Input
Note(R1=R2)
+ 220 uF
R2
1.0 f
Important: See (Note 3)
R3
1.0 f 24
Single-Ended Analog Input
Note(R3=R4)
OUT1+ OUT1-
9 12
R4
1.0 f 25
Full-Bridge Output Filter
(Note 1)
RL 6 to 8
Channel 1 Audio Output
28 31 26 1 f 10 f + 10 f + 1 f 29
PGND
11
VP
30
AGND
VP 15
0.1 f
+
220 uF
(Note 2)
18 1.0 f 0.1 f 19
CPUMP DCAP VP 5VGEN AGND PGND
17
OUT2+ 16 OUT213
VP
20 21 0.1 f 0.1 f 23
Full-Bridge Output Filter
(Note 1)
RL 6 to 8
Channel 2 Audio Output
PGND
14
2 5 1 f
V5D REF
20 K 1%
4
DGND
1. See Section 4.11 for typical full-bridge output filter. 2. Incorrectly connecting the external charge pump circuitry can result in permanent damage to the device. 3. See Section 4.1 for important information regarding using Single-Ended inputs with the CS3511. Figure 2. Typical Connection Diagram - Stereo Amplifier with Single-Ended Inputs 12 DS845F1
CS3511 4. APPLICATIONS
4.1 CS3511 Input Stage
The input stage of the CS3511 is configured as a differential receiver to maximize common-mode rejection in typical audio circuits. To maximize this benefit, the INx+ and INx- pins should be driven with differential signals from sources that have the same output impedance. Also, the signals should be routed parallel to one another from their source to the analog inputs of the CS3511. In some instances, there will be a necessity to drive the CS3511 with a single-ended input signal. In this case, the unused input should be AC coupled to ground using the same value of CI implemented for the driven channel. Either input, INx+ or INx-, can be used for the signal input. To minimize the effects of ground noise in the system, CI should be terminated at the ground connection through a resistor, RI. Please refer to Figure 3. The value of the resistor should match the output impedance of the audio source.
Audio Source CI
CS3511
INx+ ZOUT INxCI RI = ZOUT
Figure 3. CS3511 Input Stage
4.2
Dynamic DC Offset Calibration
Abrupt changes in DC output offset level are a known cause of audible turn-on and turn-off pops. Typically, when a system turns on (begins switching), the potential across the speaker changes abruptly from 0 V to the steady-state DC offset voltage of the system. Similarly, when the system turns off, the potential changes abruptly from the steady-state DC offset voltage to 0 V. These abrupt changes are heard as a pop. The CS3511 employs a patented method for reducing this pop. Immediately before the outputs begin to switch, a calibration circuit dynamically minimizes the amplifier's internal offsets. With these offsets at a minimum, the outputs begin to switch and the CS3511 begins to slowly ramp the DC output offset potential to the steady-state DC offset voltage. This ramp is slow enough to keep the speaker movement in the subsonic range. During turn-off, this procedure is reversed. The static DC offset voltage is ramped down to a dynamically minimized DC offset level before output switching is stopped. Dynamic offset cancellation requires equal impedances on the positive and negative inputs. If a single-ended audio source with a 600 output impedance is connected to the IN1+ (through a DC blocking capacitor), IN1- must be terminated to ground with a 600 resistor (also through a DC blocking capacitor. (See Figure 3).
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CS3511
4.3 CS3511 Amplifier Gain
The closed-loop gain of the CS3511 is externally configured via two input pins, GAIN0 and GAIN1. The AC Electrical Characteristics table show the four different gain values available based on the pin voltages at GAIN0 and GAIN1. The GAIN0 and GAIN1 input pins have weak internal pull-down resistors; so they should be driven high when set to a logic high. Internally, different input resistor values are used to implement the four gain settings. Thus, the input impedance will change based on the gain setting. The gain tracking is very tightly matched within each device, but the absolute input impedance will vary due to process variations. This variation must be considered when choosing the proper value of CI. The low-frequency roll-off characteristic is dedicated by the choice of CI and RI. The -3 dB frequency is: fc - 3 dB = 1 2 CI RI
On the CRD3511, a value of 1.0 F is used for CI; this value provides a nearly flat response down to 20 Hz, even for the highest gain setting. In many cases, a lower value of CI can be used due to a lower gain setting or because the speakers used do not have the ability to reproduce low-frequency signals.
4.4
MUTE Pin
The MUTE pin must be driven to a logic low or logic high state for proper operation. To enable the amplifier, connect the MUTE pin to a logic low. To enable the mute function, connect the MUTE pin to a logic high signal. When in mute, the internal processor bias voltages remain active in the CS3511. This state maintains the bias on the input coupling capacitor to prevent audible transients which would be caused by the charging and discharging of this capacitor. It is recommended that the MUTE pin be held high during power-up or power-down to eliminate audible transients. If power-up and/or power-down pops are present with a CS3511 amplifier, the cause may be other circuitry external to the CS3511, such as an audio processor or preamp. If the CS3511 is in the active state (MUTE pin is low), these audible pops will be amplified and output to the speakers. To eliminate this problem, activate the MUTE pin before the power supply collapses during a power-down sequence.
4.5
SLEEP Pin
When pulled high, the SLEEP pin puts the device into a low quiescent current mode. To disable sleep mode, the SLEEP pin should be grounded. While the device is in low power mode the STATUS pin will be in a logic high state to indicate that the device is not ready to produce audio.
4.6
Power Up and Power Down Sequence
To minimize power-on and power-off transients, the device should be held in the MUTE state while powering up or powering down the CS3511. The SLEEP pin can be held in either the logic high state or logic low state during power-up or power-down.
4.6.1
Recommended Power-Up Sequence
1. Apply power to the system. 2. Hold the MUTE pin in the logic high state until the power supply is stable. In this state, all associated outputs are held in a high-impedance state. 3. Set the MUTE pin to a logic low state to begin normal operation. If the SLEEP pin is held high during power-on (optional), it should be set low before the MUTE pin is set low.
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CS3511
4.6.2 Recommended Power-Down Sequence
1. Set the MUTE pin to the logic high state. This will mute the amplifier outputs and hold them in a highimpedance state. 2. Optionally, the SLEEP pin can now be set to a logic high state to place the device into low power mode. 3. The power supplies can now be removed.
4.7
Protection Circuits
The CS3511 is protected against under-voltage, over-current, and over-temperature conditions. If one of these fault conditions are present the amplifier will be muted, the outputs will be tri-stated, and the STATUS pin will remain in a logic high state until the condition clears. The amplifier will automatically attempt to recover from a detected fault condition.
4.7.1
Under-Voltage Protection
An under-voltage fault occurs if the voltage sensed on the VP terminals, the charge pump, or on V5A drops below the corresponding falling trigger point seen in the DC Electrical Characteristics table. The under-voltage fault will automatically clear once the voltage exceeds the associated rising trigger point. V5GEN, V5A, and V5D must be connected together in order to properly monitor V5D and V5GEN. (See Figure 1 and Figure 2).
4.7.2
Over-Temperature Protection
An over-temperature fault occurs if the junction temperature of the device exceeds the rising junction thermal error trigger point seen in the AC Electrical Characteristics table. The thermal hysteresis of the device will cause the fault to automatically clear when the junction temperature drops below the falling junction thermal error trigger point.
4.7.3
Over-Current Protection
An over-current fault occurs if more current than the over-current error trigger point flows from any of the amplifier output pins, see AC Electrical Characteristics. Over current can occur if the speaker wires are shorted together, if one side of the speaker is shorted to ground, or if the speaker impedance is too low. WARNING: The outputs of the CS3511 should never be shorted to VP. Doing so can result in permanent damage to the device.
4.8
Integrated 5 V Regulator
The CS3511 includes an internal 5 V regulator in order to provide a supply to the internal digital and analog circuitry. The output of the regulator is present on the 5VGEN pin. The regulator output pin should have a bypass capacitor connected to AGND and be connected to the digital and analog supply pins as shown in the Typical Connection Diagrams in Section 3. The regulator output can be used to set the SLEEP, MUTE, GAIN0, and GAIN1 pins to a logic high state. The regulator is able to source the maximum current shown in the DC Electrical Characteristics table.
4.9
Power Dissipation De-Rating
As a result of high-efficiency and good package thermal characteristics, the CS3511 can operate at elevated ambient temperatures without having to de-rate the output power, assuming 8 output loads or higher. The exposed pad must be soldered to the PC Board to increase the maximum power dissipation capability of the CS3511 package. Soldering will minimize the likelihood of an over-temperature fault occurring during
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CS3511
continuous heavy load conditions. There should be vias for connecting the exposed pad to the copper area on the printed circuit board. The pad must be electrically connected to PGND. See Section 5.2 for more information on the thermal pad and Section 9.1 for more information on thermal dissipation for the CS3511.
4.10
Performance Measurements of the CS3511
The CS3511 operates by generating a high-frequency switching signal based on the audio input. This signal is sent through a low-pass filter (external to the CS3511 amplifier) that recovers an amplified version of the audio input. The frequency of the switching pattern is spread spectrum and typically varies between 100 kHz and 1.0 MHz, which is well above the 10 Hz - 20 kHz audio band. The pattern itself does not alter or distort the audio input signal, but it does introduce some inaudible components outside of the audio band. The measurements of certain performance parameters, particularly noise-related specifications such as THD+N, are significantly affected by the design of the low-pass filter used on the output as well as the bandwidth setting of the measurement instrument used. Unless the filter has a very sharp roll-off just beyond the audio band or the bandwidth of the measurement instrument is limited, some of the inaudible components introduced by the CS3511 amplifier's switching pattern will degrade the measurement result. One feature of the CS3511 is that it does not require large multi-pole filters to achieve excellent performance in listening tests, usually a more critical factor than performance measurements. The CRD3511 Evaluation Board uses the filter described in Section 4.11, which has a simple two-pole output filter and excellent performance in listening tests. Measurements in this data sheet were taken using this same circuit with a limited bandwidth setting in the measurement instrument.
4.11
Full-Bridge Output Filter
Figure 4 shows the output filter for a full-bridge configuration. The transient-voltage suppression circuit (snubber circuit) is comprised of a resistor (5.6 ) and capacitor (680 pF) and should be placed as close as possible to the corresponding PWM output pins to greatly reduce radiated EMI. The inductors, L1 and L2, and capacitor, C1, comprise the low-pass filter. Along with the nominal load impedance of the speaker, these values set the cutoff frequency of the filter. Table 2 shows the component values based on nominal speaker (load) impedance for a corner frequency (-3 dB point) of approximately 35 kHz.
L1 OUTx+
5.6
680 pF
C1
L2 OUTx5.6
680 pF
Figure 4. Output Filter Load
8 6
L1, L2
22 H 15 H
C1
0.47 F 0.47 F
Table 2. Low-Pass Filter Components 16 DS845F1
CS3511 5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT
5.1 Power Supply and Grounding
The CS3511 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. It is necessary to de-couple the power supply by placing capacitors directly between the power and ground of the CS3511. Decoupling capacitors should be as close to the pins of the CS3511 as possible. The lowest value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS3511 to minimize inductance effects. The CRD3511 reference design demonstrates the optimum layout and power supply arrangements.
5.1.1
Maximum Supply Voltage
The absolute maximum allowable voltage on the VP supply pins (pins 10, 15 and 20) is shown in the Absolute Maximum Ratings table. Device damage can occur above this voltage. Please note that the absolute maximum voltage does not represent a valid operating condition. The maximum voltage on the VP pins during operation is shown in the Recommended Operating Conditions table. During normal operation, the output pins (pins 9, 12, 13, and 16) may experience overshoot voltages due to inductive kickback. Care should be taken to properly de-couple the VP pins because overshoot on the output pins can travel through the CS3511 output devices and appear on the VP pins. Without proper power supply decoupling, this can cause ripple voltages on the VP pins that might exceed their absolute maximum voltage shown in the Absolute Maximum Ratings table. However, this will only happen in extreme cases and can be prevented by placing the high-frequency decoupling capacitors close to the VP pins.
5.2
QFN Thermal Pad
The CS3511 is available in a compact QFN package. The underside of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to PGND. A series of thermal vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers; the copper in these ground planes will act as a heat sink for the CS3511. The CRD3511 reference design demonstrates the optimum thermal pad and via configuration.
5.3
Layout Considerations
The CS3511 is a power (high current) amplifier that operates at relatively high switching frequencies. The outputs of the amplifier switch between the supply voltage and ground, at high speeds, while driving high currents. This high-frequency digital signal is passed through an LC low-pass filter to recover the amplified audio signal. Since the amplifier must drive the inductive LC output filter and speaker loads, the amplifier outputs can be pulled above the supply voltage and below ground by the energy in the output inductance. Additionally, the CS3511's junction temperature rises when supplying power to loads and relies on the PCB for heat sinking. To avoid subjecting the CS3511 to potentially damaging voltage stress and output-power-limiting elevated junction temperatures, it is critical to have a good printed circuit board layout. It is strongly recommended that the Cirrus CRD3511 layout be used for all applications and only be deviated from after careful analysis of the effects of any changes. Please refer to Cirrus Logic application note AN315 for further information regarding the layout of the CS3511.
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CS3511 6. TYPICAL AUDIO PERFORMANCE PLOTS
Test Conditions (unless otherwise specified): All plots were taken using the CRD3511 Reference Design Board sourced with a differential input; TA = 25C; 10 Hz to 20 kHz Measurement Bandwidth; Performance measurements taken with a 997 Hz sine wave and AES17 measurement filter; GAIN1 = 0, GAIN0 = 1; VP = 12 VDC.
10
10
5
5
2
2
12.0 V
1
12.0 V
1
0.5 % 0.2
0.5 % 0.2
9.0 V
0.1
9.0 V
0.1 0.05
0.05
0.02
0.02
0.01 10m
20m
50m
100m
200m
500m W
1
2
5
10
20
0.01 10m
20m
50m
100m
200m
500m W
1
2
5
10
20
Figure 5. THD+N vs. Output Power (RL= 8 )
10
10
Figure 6. THD+N vs. Output Power (RL= 6 )
5
5
2
2
1
1
0.5
0.5
% 0.2
% 0.2
0.1
10 kHz
0.1
10 kHz 1 kHz
0.05
100 Hz
0.02
1 kHz
0.05
100 Hz
0.02
0.01 0.007 10m 20m 50m 100m 200m 500m W 1 2 5 10 20
0.01 0.007 1m 2m 5m 10m 20m 50m 100m W 200m 500m 1 2 5 10 20
Figure 7. THD+N vs. Output Power (RL= 8 )
10
10
Figure 8. THD+N vs. Output Power (RL= 6 )
5
5
2
2
1
1
0.5 % 0.2
%
0.5
0.2
0.1
GAIN=01
GAIN=10 GAIN=11
0.1
GAIN=01 GAIN=10 GAIN=11
0.05
0.05
0.02
0.02
GAIN=00
0.01 10m 20m 50m 100m 200m 500m W 1 2 5 10 20
0.01 10m
GAIN=00
20m 50m 100m 200m 500m W 1 2 5 10 20
Figure 9. THD+N vs. Output Power (RL= 8 )
Figure 10. THD+N vs. Output Power (RL= 6 )
18
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CS3511
2.5
2.5
2 Supply Current (A)
2
Supply Current (A)
1.5
1.5
1
1
0.5
0.5
0 0 2 4 6 8 10 12 14 16 18 20 Total Output Power (Watts)
0 0 2 4 6 8 10 12 14 16 18 20 Total Output Power (Watts)
Figure 11. Supply Current vs. POUT (RL= 8 )
10 5 10 5
Figure 12. Supply Current vs. POUT (RL= 6 )
2 1 0.5
2 1 0.5
0.2
5.0 W 1.0 W
%
0.2 0.1 0.05
5.0 W 1.0 W
%
0.1 0.05
0.02 0.01 0.005
0.02 0.01 0.005
0.5 W
0.5 W
0.002
0.002
0.001 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
0.001 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 13. THD+N vs. Frequency (RL= 8 )
+5
Figure 14. THD+N vs. Frequency (RL= 6 )
+5
+4
+4
+3
+3
+2
+2
+1 d B r A -1
+1 d B r A -1
-0
-0
-2
-2
-3
-3
-4
-4
-5 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
-5 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 15. Frequency Response (POUT = 1 W, RL= 8 )
Figure 16. Frequency Response (POUT = 1 W, RL= 6 )
See Note below. Note: The full-bridge output filter found on the CRD3511 reference design board implements 22H inductors and is optimized for an 8 load.
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CS3511
-40 -40
-60
-60
-80
-80
d B
CH2 to CH1
-100
d B
CH2 to CH1
-100
CH1 to CH2
-120
CH1 to CH2
-120
-140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
-140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 17. Crosstalk vs. Frequency (RL= 8 )
+20
+20
Figure 18. Crosstalk vs. Frequency (RL= 6 )
+0
+0
-20
-20
-40
-40
d B V
-60
d B V
-60
-80
-80
-100
-100
-120
-120
-140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
-140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 19. Output FFT (POUT = 1 W, RL= 8 )
Figure 20. Output FFT (POUT = 1 W, RL= 6 )
+20
+20
+0
+0
-20
-20
-40
-40
d B V
-60
d B V
-60
-80
-80
-100
-100
-120
-120
-140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
-140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 21. Output FFT (POUT = 5 W, RL= 8 )
Figure 22. Output FFT (POUT = 5 W, RL= 6 )
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CS3511
100 90 80 70
100 90 80 70
Efficiency (%)
Efficiency (%)
60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 10 Output Power Per Channel (Watts)
60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 10 Output Power Per Channel (Watts)
Figure 23. Efficiency (RL= 8 )
Figure 24. Efficiency (RL= 6 )
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CS3511 7. PARAMETER DEFINITIONS
Signal to Noise Ratio (SNR) The ratio of the RMS value of the output signal, where Pout is equivalent to the specified output power at THD+N<1%, to the RMS value of the noise floor with no input signal applied and measured over the specified bandwidth, typically 20 Hz to 20 kHz. Expressed in decibels. Dynamic Range (DYR) The ratio of the RMS value of the output signal produced when Pout is equivalent to the specified output power at THD+N<1% to the RMS sum of all other spectral components over the specified bandwidth, typically 20 Hz to 20 kHz. Dynamic Range is a signal-to-noise ratio measurement made with a -60 dBi input signal where dBi is referenced to the input signal amplitude resulting in the specified output power at THD+N<1%. This technique ensures that the distortion components are below the noise level and do not effect the measurement. Expressed in decibels. Total Harmonic Distortion + Noise (THD+N) The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
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DS845F1
CS3511 8. PACKAGE DIMENSIONS 32L QFN (6 X 6 mm BODY) PACKAGE DRAWING
D b e Pin #1 Corner
Pin #1 Corner
E
E2
A1 A Top View Side View
L
D2
Bottom View
DIM
A A1 A3 b D D2 E E2 e L
MIN
0.031 0.00 0.008 0.177 0.177 0.014
INCHES NOM
0.033 -0.008 REF 0.010 0.2362 BSC 0.181 0.2362 BSC 0.181 0.026 BSC 0.016
MAX
0.035 0.05 0.012 0.185 0.185 0.018
MIN
0.80 0.00 0.20 4.50 4.50 0.35
MILLIMETERS NOM
0.85 -0.203 REF 0.25 6.00 BSC 4.60 6.00 BSC 4.60 0.65 BSC 0.40
NOTE MAX
0.90 0.05 0.30 4.70 4.70 0.45 1 1 1,2 1 1 1 1 1 1
JEDEC #: MO-220 Controlling Dimension is Millimeters. 1. Dimensioning and tolerance per ASME Y 14.5M-1994. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip.
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CS3511 9. THERMAL CHARACTERISTICS
Parameter
Junction to Case Thermal Impedance
Symbol
JC
Min
-
Typ
1
Max
-
Units
C/Watt
9.1
Thermal Flag
This device is designed to have the metal flag on the bottom of the device soldered directly to a metal plane on the PCB. To enhance the thermal dissipation capabilities of the system, this metal plane should be coupled with vias to a large metal plane on the backside (and inner ground layer, if applicable) of the PCB. In either case, it is beneficial to use copper fill in any unused regions inside the PCB layout, especially those immediately surrounding the CS3511. In addition to improving in electrical performance, this practice also aids in heat dissipation. The heat dissipation capability required of the metal plane for a given output power can be calculated as follows: CA = [(TJ(MAX) - TA) / PD] - JC where, CA = Thermal resistance of the metal plane in C/Watt TJ(MAX) = Maximum rated operating junction temperature in C, equal to 150 C TA = Ambient temperature in C PD = RMS power dissipation of the device, equal to 0.176*PRMS-OUT (assuming 85% efficiency) JC = Junction-to-case thermal resistance of the device in C/Watt, equal to 1 C/Watt
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CS3511 10.ORDERING INFORMATION
Product
CS3511
Description
Stereo, 10W High-Efficiency Class-D Audio Amplifier 2 x 10 W, 4 Layer / 1 oz. Copper Reference Design
Package Pb-Free
32-QFN Yes
Grade
Temp Range Container
Rail Tape and Reel -
Order#
CS3511-CNZ CS3511-CNZR CRD3511-Q1
Commercial -10 to +70C
CRD3511-Q1
-
-
-
-
DS845F1
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CS3511 11.REVISION HISTORY
Release
F1 - - - - -
Changes
Updated Channel Separation on front page. Updated Output Power, Channel Separation, and Efficiency specifications in "AC Electrical Characteristics" table on page 7. Added Single Ended performance data in the "AC Electrical Characteristics" table on page 7. Updated 5VGEN DC Current Source specification in "DC Electrical Characteristics" table on page 9. Added Note 9 on page 8.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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DS845F1

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